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DEVICE SPECIFICATION
SONET/SDH/ATM OC-48 8:1 TRANSMITTER BiCMOS LVPECL OC-48 TRANSMITTER AND CLOCK GENERATOR SONET/SDH/ATM OC-12 8:1 TRANSMITTER RECEIVER GENERAL DESCRIPTION
S3041 S3041 S3041
FEATURES
* Micro-power Bipolar technology * Complies with Bellcore and ITU-T specifications * On-chip high-frequency PLL for clock generation * Supports 2.488 GHz (OC-48) * Reference frequency of 155.52 MHz * 8-bit LVDS data path * Compact 100 TQFP/TEP package * Diagnostic loopback mode * Line loopback * Lock detect * Low jitter LVPECL interface * Single 3.3V supply
The S3041 SONET/SDH Mux chip is a fully integrated serialization SONET OC-48 (2.488 GHz) interface device. The chip performs all necessary parallel-to-serial and clock synthesis functions in conformance with SONET/SDH transmission standards. The device is suitable for SONET-based ATM applications. Figure 1 shows a typical network application. On-chip clock synthesis PLL components are contained in the S3041 Mux chip allowing the use of a slower external transmit clock reference. The chip can be used with a 155.52 MHz reference clock, in support of existing system clocking schemes. The low jitter LVPECL interface guarantees compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3041 is packaged in a 100 TQFP/TEP, offering designers a small package outline.
APPLICATIONS
* * * * * * * * * SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment ATM over SONET/SDH Section repeaters Add drop multiplexers Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
Figure 1. System Block Diagram
8 8 8 8
Network Interface Processor
8
S3045
S3041 8 S3042
OTX
8 8 8 8 8
S3045
ORX
S3040
S3042
8
8 8 8 8 8 8 8
8 S3040 ORX OTX S3041
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Network Interface Processor
1
S3041 S3041 OVERVIEW
The S3041 Mux implements SONET/SDH serialization and transmission functions. The block diagram in Figure 2 shows basic operation of the chip. This chip can be used to implement the front end of SONET equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip includes parallel-to-serial conversion and system timing. The system timing circuitry consists of a high-speed phase detector, clock dividers, and clock distribution throughout the front end.
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
The sequence of operations is as follows:
Transmitter Operations: 1. 8-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Internal clocking and control functions are transparent to the user. Details of data timing can be seen in Figures 7 through 10. Suggested Interface Devices
AMCC AMCC AMCC S3040 S3045 S3042 OC-48 Clock Recovery Device OC-48 to OC-12 Demux OC-48 Demux
Figure 2. S3041 Functional Block Diagram
DLEB LLDP/N LLCLKP/N LLEB LSDP/N PINP/N[7:0] PICLKP/N READP/N M U X TIMING GEN 16
FIFO
PULSE0P/N
8:1 PARALLEL TO SERIAL
M U X
D
TSDP/N
LSCLKP/N TSCLKP/N PCLKP/N 77MCK
KILLTXCLKN TESTEN VCO, CLOCK DIVIDER and PHASE DETECTOR REFCLKP/N RSTB CAP1/2 LOCKDET
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard for connecting one fiber system to another at the optical level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for fiber interconnect between telephone networks of different countries. SONET is capable of accommodating a variety of transmission rates and applications. The SONET standard is a layered protocol with four separate layers defined. These are: * Photonic * Section * Line * Path Figure 3 shows the layers and their functions. Each of the layers has overhead bandwidth dedicated to administration and maintenance. The photonic layer simply handles the conversion from electrical to optical and back with no overhead. It is responsible for transmitting the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this layer are framing, scrambling, and error monitoring. The line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates. Figure 4 shows a standard OC-48 Frame former structure. Data Rates and Signal Hierarchy
S3041
Table 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the basic SONET signal referred to as the synchronous transport signal level-1 (STS-1). An STS-N signal is made up of N byte-interleaved STS-1 signals. The optical counterpart of each STS-N signal is an optical carrier level-N signal (OC-N). The S3041 chip supports OC-48 rate (2.488 Gbps).
Figure 3. SONET Structure
Functions
Payload to SPE mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Path layer Line layer Section layer
Path layer Line layer Section layer
Photonic layer
Photonic layer
End Equipment
Fiber Cable End Equipment
Table 1. SONET Signal Hierarchy
Elec.
STS-1 STS-3 STS-12 STS-24 STS-48
CCITT
STM-1 STM-4 STM-8 STM-16
Optical Data Rate (Mbps)
OC-1 OC-3 OC-12 OC-24 OC-48 51.84 155.52 622.08 1244.16 2488.32
Figure 4. STS-48/OC-48 Frame Format
A1 A1 9 Rows A1 A1 48 A1 Bytes A2 A2 A2 A2 48 A2 Bytes
Transport Overhead 144 Columns 144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns 4176 x 9 = 37,584 bytes s
125 sec
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s
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S3041 S3041 ARCHITECTURE/FUNCTIONAL DESIGN
Mux Operation
The S3041 performs the serializing stage in the processing of a transmit SONET STS-48 bit serial data stream. It converts the byte serial 311 Mbyte/sec data stream to bit serial format at 2.488 Gbps. Diagnostic loopback is provided (transmitter to receiver), and Line Loopback is also provided (receiver to transmitter). A high-frequency bit clock is generated from a 155.52 MHz frequency reference by using a frequency synthesizer consisting of an on-chip phase-locked loop circuit with a divider. Clock Divider and Phase Detector The Clock Divider and Phase Detector, shown in the block diagram in Figure 2, contains monolithic PLL components. The REFCLK input must be generated from a differential LVPECL crystal oscillator which has a frequency accuracy of better than 20 ppm in order for the VCOCLK frequency to have the same accuracy required for operation in a SONET system. In order to meet the .01 UI SONET jitter specifications, the maximum reference clock jitter must be guaranteed over the 12 KHz to 20 MHz bandwidth. For details of reference clock jitter requirements, see Table 2.
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Timing Generator The Timing Generator function, seen in Figure 2, provides two separate functions. It provides a byte rate version of the TSCLK, and a mechanism for aligning the phase between the incoming byte clock and the clock which loads the parallel-to-serial shift register. The PCLK output is a byte rate version of TSCLK. For STS-48, the PCLK frequency is 311 MHz. PCLK is intended for use as a byte speed clock for upstream multiplexing and overhead processing circuits. Using PCLK for upstream circuits will ensure a stable frequency and phase relationship between the data coming into and leaving the S3041 device. In the parallel-to-serial conversion process, the incoming data is passed from the PICLK byte clock timing domain to the internally generated byte clock timing domain, which is phase aligned to TSCLK. The Timing Generator also produces a feedback reference clock to the Phase Detector. A counter divides the synthesized clock down to the same frequency as the reference clock REFCLK. Parallel-to-Serial Converter The FIFO is used to accomodate phase differences between the internal byte clock and the external PICLK. The READ and PULSE signals are used to control the FIFO to prevent overflow/underflow conditions. The Parallel-to-Serial converter shown in Figure 2 is comprised of a FIFO and a parallel-to-serial register. The FIFO latches the data from the PIN[7:0] bus on the rising edge of PICLK. The parallel-to-serial register is a parallel loadable shift register which takes its parallel input from the FIFO. An internally generated byte clock, which is phase aligned to the transmit serial clock as described in the Timing Generator description, activates the parallel data transfer between registers. The serial data is shifted out of the second register at the TSCLK rate.
Table 2. Reference Jitter Limits
Maximum Reference Clock Jitter in 12 kHz to 20 MHz Band 1 ps rms Operating Mode STS-48
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Table 3. Input Pin Assignment and Description
Pin Name PINP7 PINN7 PINP6 PINN6 PINP5 PINN5 PINP4 PINN4 PINP3 PINN3 PINP2 PINN2 PINP1 PINN1 PINP0 PINN0 PICLKP PICLKN Level LVDS I/O I Pin # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 47 48 Description
S3041
Parallel Data Input. A 311 Mbyte/sec word, aligned to the PICLK parallel input clock. PIN<7> is the most significant bit (corresponding to bit 1 of each PCM word, the first bit transmitted). PIN<0> is the least significant bit (corresponding to bit 8 of each PCM word, the last bit transmitted). PIN<7:0> is sampled on the rising edge of PICLK.
LVDS
I
Parallel Input Clock. A 311 MHz nominally 50% duty cycle input clock, to which PIN<7:0> is aligned. PICLK is used to transfer the data on the PIN inputs into a holding register in the parallel-toserial converter. The rising edge of PICLK samples PIN<7:0>. Line Loopback Data. Inputs normally provided from a companion S3042 device. Used to implement a line loopback function in which the receive serial data and clock signals are regenerated and passed through the S3041 transmitter. Line Loopback Clock. Inputs normally provided from a companion S3042 device. Used to implement a line loopback function in which the receive serial data and clock signals are regenerated and passed through the S3041 transmitter. Reference Clock. 155.52 MHz. The clock generator circuit will lock to this reference clock by comparing the REFCLK with an internally divided down clock. Diagnostic Loopback Enable. Active Low. When active, selects diagnostic loopback. The primary data (TSD) and clock (TSCLK) are always active. When active, the diagnostic loopback clock, (LSCLK), and data (LSD) outputs are active. Master Reset. Reset input for the device, active low. During reset, PCLK does not toggle. Line Loopback Enable. Active Low. Selects Line Loopback when active. When LLEB is active, the S3041 will route the data from the LLD/LLCLK inputs to the TSD/TSCLK outputs. Inactive for normal operation.
LLDP LLDN
Externally Biased Diff. LVPECL Externally Biased Diff. LVPECL Internally Biased Diff. LVPECL
I
58 57
LLCLKP LLCLKN
I
62 61
REFCLKP REFCLKN
I
80 81
DLEB
LVTTL
I
65
RSTB LLEB
LVTTL LVTTL
I I
64 68
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S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Table 3. Input Pin Assignment and Description (Con't.)
Pin Name READP READN Level LVDS I/O I Pin # 20 21 Description Elastic Store Write Differential Input. This input pin is clocked in using the rising edge of PICLK clock. This input is used to align the elastic store. The S3041 mux will monitor the READ input for a fault condition. If there is no activity or stuck high more than one pulse every twelfth 311 MHz clock cycle, a fault condition will be declared. The PULSE0 signal will output two 311 MHz pulse width instead of one every sixth 311 MHz clock cycle. Kill Transmit Clock Input. In normal operation, the KILLTXCLKN should be set High. When this input is Low, it will force the PCLK and PULSE0 outputs Low. Test Clock Enable.When this input is High, it will select the LLCLK input instead of the internally generated 2.488 GHz clock as the system clock. When this input is Low, it will select the internally generated 2.488 GHz clock. For normal operation, set low. External loop filter capacitor pins. The loop filter capacitor and resistors are connected to these pins. (See Figure 18).
KILLTXCLKN
LVTTL
I
69
TESTEN
LVTTL
I
60
CAP1 CAP2
Analog
I
94 93
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Table 4. Output Pin Assignment and Description
Pin Name TSCLKP TSCLKN TSDP TSDN PCLKP PCLKN LSDP LSDN Level Diff. CML Diff. CML LVDS I/O O Pin # 7 8 11 12 45 46 67 66 Description
S3041
Transmit Clock output. Transmit serial clock that can be used to retime the TSD signal. An optical transmitter can use the rising edge of TSCLK to retime the TSD data. Transmit Serial Data. Serial data stream signals, normally connected to an optical transmitter module. Parallel Clock. A reference clock generated by dividing the internal bit clock by eight. It is normally used to coordinate byte-wide transfers between upstream logic and the S3041 device. Loopback Serial Data. Serial data stream signals normally connected to a companion S3042 device for diagnostic loopback purposes. The LSD outputs are updated on the rising edge of the LSCLK. Loopback Serial Clock. Serial clock signals normally connected to a companion S3042 device for diagnostic loopback purposes. The LSD outputs are updated on the rising edge of the LSCLK. 77 MHz Clock Output. 77 MHz clock output from the clock synthesizer. Elastic Store Read Differential Outputs. This output pulse is sychronized with the falling edge of PCLKP/N. This signal is used to align the elastic store. The PULSE0 output should be active for only one pulse every twelfth 311 MHz clock cycle during the normal (no fault) operation. If the S3041 mux detects no activity or stuck high more than one pulse every twelfth 311 MHz on the READ input, a fault condition will be declared. The S3041 mux will output a two 311 MHz pulse width instead of one every sixth 311 MHz clock cycle. Lock Detect. Goes Low after the PLL has locked to the clock provided on the REFCLK pins. LOCKDET is an asynchronous output.
O O
Low Swing Diff. CML Low Swing Diff. CML LVTTL LVDS
O
LSCLKP LSCLKN
O
75 74
77MCK PULSE0P PULSE0N
O O
51 22 23
LOCKDET
LVTTL
O
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S3041
Table 5. Common Pin Assignment and Descriptions
Pin Name COREGND Level GND I/O Pin # 1, 2, 15, 83, 96, 98, 99 3, 4, 16, 90, 97, 100
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Description Core Ground
COREVCC
+3.3V
Core VCC
CMLVCC CMLGND
+3.3V GND
5, 14, 72, CML VCC 73, 76, 77 6, 13, 63, 70, 71, 78, 79, 18 52 53 24 25 27 28 55 56 54 CML Ground
TTLVCC TTLGND LVDSGND LVDSVCC PECLVCC PECLGND AVCC AGND NC
+3.3V GND GND +3.3V +3.3V GND +3.3V GND
TTL VCC TTL Ground LVDS Ground LVDS VCC PECL VCC PECL Ground
84, 88, 91 Analog VCC 85, 89, 92 Analog Ground 9, 10, 17, 26, 49, 50, 59, 82, 86, 87, 95 Not Connected
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Figure 5. S3041 Pinout
S3041
COREGND COREGND COREVCC COREVCC CMLVCC CMLGND TSCLKP TSCLKN NC NC TSDP TSDN CMLGND CMLVCC COREGND COREVCC NC TTLVCC LOCKDET READP READN PULSE0P PULSE0N LVDSGND LVDSGND
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
COREVCC COREGND COREGND COREVCC COREGND NC CAP1 CAP2 AGND AVCC COREVCC AGND AVCC NC NC AGND AVCC COREGND NC REFCLKN REFCLKP CMLGND CMLGND CMLVCC CMLVCC
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NC LVDSVCC LVDSVCC PINP7 PINN7 PINP6 PINN6 PINP5 PINN5 PINP4 PINN4 PINP3 PINN3 PINP2 PINN2 PINP1 PINN1 PINP0 PINN0 PCLKP PCLKN PICLKP PICLKN NC NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
S3041 Pinout Top View
100 TQFP/TEP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LSCLKP LSCLKN CMLVCC CMLVCC CMLGND CMLGND KILLTXCLKN LLEB LSDP LSDN DLEB RSTB CMLGND LLCLKP LLCLKN TESTEN NC LLDP LLDN PECLVCC PECLVCC PECLGND TTLGND TTLGND 77MCK
9
S3041
Figure 6. 100 TQFP/TEP Package
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
TOP VIEW
Thermal Management
Device S3041 Max Power 1.6 W ja 26C/W Comments Required air flow of 100 LFPM or with DW0045-28 heatsink.
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER OTHER OPERATING MODES
Diagnostic Loopback When the Diagnostic Loopback Enable (DLEB) input is active, the differential serial clock and data outputs are enabled. A loopback from the transmitter to the receiver at the serial data rate can be set up for diagnostic purposes. Line Loopback
S3041
The Line Loopback circuitry consists of alternate clock and data inputs. For the S3041, it selects the source of the data and clock which is output on TSD and TSCLK. When the Line Loopback Enable input (LLEB) is high, it selects data and clock from the Parallel to Serial Converter block. When LLEB is low, it forces the output data multiplexer to select data and clock from the LLD and LLCLK inputs, and a receive-to-transmit loopback can be established at the serial data rate. Both Diagnostic and Line Loopback can be active at the same time.
Table 6. Performance Specifications
Parameter Nominal VCO Center Frequency Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle Reference Clock Rise & Fall Times Min Typ 2.488 12% -20 45 +20 55 1.5 Max Units MHz pp m % ns 20% to 80% of amplitude. Required to meet SONET output frequency specification. Condition
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S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Table 7. Output Jitter Generation vs. Ambient Temperature with Heatsink (DW0045-28) and 100 LFPM
Temperature Voltage -40 C 25 C 70 C 85 C 3.1 0.006 0.007 0.007 0.007 Jitter Generation 3.3 0.006 0.006 0.007 0.007 3.47 0.006 0.006 0.007 0.007 Unit V UI UI UI UI
Table 8. Output Jitter Generation vs. Ambient Temperature in Still Air
Temperature Voltage -40 C 25 C 70 C 85 C 3.1 0.006 0.007 0.008 0.008 Jitter Generation 3. 3 0.006 0.007 0.007 0.008 3.47 0.006 0.007 0.007 0.008 Unit V UI UI UI UI
Note: Data were taken with 100 sweeps on HP test equipment.
Table 9. LVTTL Input/Output DC Characteristics
Symbol VIH VIL IIH IIL VOH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage -500 2.2 Min 2.0 0.0 Typ Max TTL VCC 0.8 50 Unit V V A A V Conditions TTL VCC = Max TTL VCC = Max VIN = 2.4 V VIN = 0.5 V VIH = Min. VIL = Max. IOH = -100 A VIH = Min. VIL = Max. IOL = 4 mA
VOL
Output Low Voltage
0.5
V
Note: All parameters are specified with respect to the source termination and ground with VTTL = Max. = 3.465V.
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Table 10. LVDS Input/Output DC Characteristics1
Symbol VIH VIL VINDIFF 2 VINSINGLE RDIFF IIH IIL VKH VKL VOH VOL VOUTDIFF 2 VOUTSINGLE Description Input High Voltage Input Low Voltage Input Voltage Differential Input Single-ended Voltage Differential Input Resistance Input High Current Input Low Current High I/O Clamp Voltage Low I/O Clamp Voltage Output High Voltage Output Low Voltage Output Differential Voltage Output Single-ended Voltage -10 0.15 -0.15 1.00 .700 460 230 740 370 1.5 -1.5 1.80 1.40 900 450 Min 1.1 .9 20 0 100 80 100 Typ Max 1.7 1.5 900 450 120 +10 Unit V V mV mV A A V V V V mV mV Conditions VLVDSVCC = Max VLVDSVCC = Max VLVDSVCC = Max VLVDSVCC = Max VLVDSVCC = Max VIN = Max VIN = VLVDSVCC
S3041
II = Io = +100A VLVDSVCC = 0V II = Io = -100A VLVDSVCC = 0V VIH = Min VIL = Max VIH = Min VIL = Max VIH = Max VIL = Min VIH = Max VIL = Min
Note: Output loading is 220 to GND and 100 line-to-line. 1. All parameters are specified with respect to the source termination and ground with VTTL = Max. = 3.465V. 2. See Figure 11.
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S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Table 11. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on VCC with Respect to GND Voltage on any LVPECL Input Pin ICC 3.13 VCC -2 39 0 3.3 Min -40 Typ Max 85 +130 3.47 VCC 455 Units C C V V mA
Table 12. Absolute Maximum Ratings
Parameter Storage Temperature Voltage on VCC with Respect to GND Voltage on any LVPECL Input Pin High Speed LVPECL Output Source Current Min -65 -0.5 0 Typ Max 150 +4.0 VCC 50 Units C V V mA
ESD Ratings The S3041 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 500 V except pin 57, pin 58, pin 61, pin 62, pin 92, and pin 94.
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Table 13. Differential CML Output DC Characteristics
S3041
Typ Max VCC -0.55 VCC -0.10 1300 650 Units V V mV mV Condition 100 line-to-line. 100 line-to-line. 100 line-to-line. See Figure 11. 100 line-to-line. See Figure 11.
Parameter VOL VOH VOUTDIFF VOUTSINGLE
Description CML Output LOW Voltage CML Output HIGH Voltage CML Serial Output Differential Voltage Swing CML Serial Output Singleended Voltage Swing
Min VCC -0.95 VCC -0.35 560 280
Table 14. Low Swing Differential CML Output DC Characteristics
Parameters VOL VOH VOUTDIFF VOUTSINGLE Description Low Swing CML Output LOW Voltage Low Swing CML Output HIGH Voltage Low Swing CML Serial Output Differential Voltage Swing Low Swing CML Serial Output Single-ended Voltage Swing Min VCC -0.50 VCC -0.20 360 180 Typ Max VCC -0.25 VCC -0.05 800 400 Units V V mV mV Conditions 100 line-to-line. 100 line-to-line. 100 line-to-line. See Figure 11. 100 line-to-line. See Figure 11.
Table 15. Internally Biased Differential LVPECL Input DC Characteristics
Parameters VINDIFF VINSINGLE RDIFF Description Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Min 300 150 80 100 Typ Max 1200 600 120 Units mV mV Conditions See Figure 11. See Figure 11.
Table 16. Externally Biased Differential LVPECL Input DC Characteristics
Parameters VBIAS VIL VIH VINDIFF VINSINGLE RDIFF Description LVPECL DC Bias Voltage LVPECL Input LOW Voltage LVPECL Input HIGH Voltage Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Min VCC -1.2 VCC -2.000 VCC -1.20 300 150 80 100 Typ Max VCC -0.8 VCC -0.25 VCC -0.05 1200 600 120 Units V V V mV mV See Figure 11. See Figure 11. Conditions Inputs open.
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S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Figure 7. Line Loopback Input Timing Diagram
LLCLKP tSLLD LLDP/N
Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
tHLLD
Table 17. AC Transmitter Timing Characteristics
Symbol Description TSCLK/LSCLK Frequency (nom. 2.488 GHz) TSCLK/LSCLK Duty Cycle PICLK Duty Cycle tSPIN tHPIN tPTSD tSTSD tHTSD tSLLD tHLLD READP/N PIN [7.0] Set-up Time w.r.t. PICLK READP/N PIN [7.0] Hold Time w.r.t. PICLK TSCLK/LSCLK Low to TSD/LSD Valid Propagation Delay TSD/LSD Set-up Time w.r.t. TSCLK/LSCLK TSD/LSD Hold Time w.r.t. TSCLK/LSCLK LLDP/N Set-up Time w.r.t. LLCLKP/N LLDP/N Hold Time w.r.t. LLCLKP/N 77MCK Duty Cycle 77MCK Output rise and fall times (10pf load) LVDS Output rise and fall times (20-80% 275 to GND and 100 line-to-line) CML Output rise and fall times (20-80% 100 line-to-line) Low Swing CML Output rise and fall times (20-80% 100 line-to-line) tPPICLK tPPRCLK tSPULSE tHPULSE PICLK Delay from PCLK Read Delay from Pulse PULSE0 Set-up Time w.r.t. PCLK PULSE0 Hold Time w.r.t. PCLK 0 0 1 1 40 33 0.5 0.5 -100 125 100 100 100 40 60 2.1 800 150 150 13 13 + 100 Min Max 2.6 60 67 Units GHz % % ns ns ps ps ps ps ps % ns ps ps ps ns ns ns ns
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Figure 8.
S3041
PCLK
tPPICLK
PICLK
tSPULSE tHPULSE
PULSE tPPRCLK tHPIN
READ
tSPIN
tSPIN PIN[15:0]
tHPIN
VALID DATA 1
VALID DATA 2
VALID DATA 3
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S3041
Figure 9. Pin AC Input Timing
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Figure 10. Output Timing
TSCLKP/ LSCLKP
tS PIN tHPIN
PICLK
tP TSD
tS
TSD
tH
TSD
PIN[3:0]
TSD/LSD
1. When a set-up time is specified on LVDS signals between an input and a clock, the set-up time is the time in picoseconds from the cross-over point of the input to the cross-over point of the clock. 2. When a hold time is specified on LVDS signals between an input and a clock, the hold time is the time in picoseconds from the cross-over point of the clock to the cross-over point of the input.
Notes on High-Speed CML Output Timing 1. Output propagation delay time is the time in nanoseconds from the cross-over point of the reference signal to the cross-over point of the output.
Figure 11. Differential Voltage Measurement
Single-ended swing
V SINGLE
V DIFF = 2X Single-ended swing
Figure 12. S3045 LVDS Driver to S3041 LVDS Input Direct Coupled Termination
+3.3V
+3.3V
100
S3045 311DATOUT 311CLKOUT READ
S3041 PIN (7:0) PICLK READ
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SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Figure 13. S3041 CML Output to +5V PECL Input AC Coupled Termination
VCC -1.3V (DC AVG)
S3041
+3.3V 0.01 F
+5V
100 0.01 F S3041 TSDP/N TSCLKP/N
VCC -1.3V (DC AVG)
S3049 TD TDCLK
Figure 14. S3041 to S3042 for Diagnostic Loopback
+3.3V
+3.3V
100
S3041 LSDP/N LSCLKP/N
S3042 LSDP/N LSCLKP/N
Figure 15. Single-Ended LVPECL Driver to S3041 Input AC Coupled Termination
VCC -0.70V (DC AVG) +3.3V
Vcc 0.01F 300 0.01F
60
VCC -0.70V (DC AVG) Single-Ended Driver S3041 REFCLKP/N
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S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Figure 16. +5V Differential PECL Driver to S3041 Input AC Coupled Termination
+5V 0.01F 330 330
VCC -0.70V (DC AVG) +3.3V
100 0.01F
VCC -0.70V (DC AVG) S3041 REFCLKP/N
Figure 17. S3041 to S3045 Terminations
+3.3V
+3.3V 275 275
100
S3041 PULSE PCLK
S3045 PULSE 311TCLK
Figure 18. External Loop Filter Components
2.2 F 62 CAP1 62 CAP2
20
January 7, 2000 / Revision G
APPLICATION NOTE
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
S3041
The S3041 utilizes a unique elastic store buffer which can be set in two different configurations allowing the system designer to be flexible in the way a system is to be layed out. The configuration of the elastic store buffer is dependent upon the I/O pins which comprise the Synch Timing loop. This loop is formed from PULSE(I/P) to READ(O/P) and PCLK(I/P) to PICLK(O/P). The elastic store buffer can be thought of as a memory stack with a read pointer. The PULSE signal is the read pointer which announces that it has read a register and when fed back to READ input, it synchronizes the write operation of the buffer so as not to simultaneously write over the same register that it has read previously.
Figure 19.
OSCILLATOR
REFCLK P/N
311 TCLK 311 CLKOUT
PCLK P/N PICLK P/N
PLL
DIV
311 DATOUT
8
PIN[7:0] FIFO
PULSE D READ Q PULSE READ
CUSTOMER LOGIC/ S3045
S3041
In the figure shown above, we are using the second configuration of the elastic store buffer. This configuration fully utilizes the elastic store buffer and allows the user a delay accommodation of 0 to 13ns. The PULSE delay must follow the PCLK delay. It is very important that the relationship between these two signals be kept all the way through the loop. Otherwise it is possible to under or over spill the buffer. It is important to insure that the PULSE signal is retimed along with the outgoing data to the S3041.
January 7, 2000 / Revision G
21
S3041
Figure 20. Typical Eye Opening for TSD
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
22
January 7, 2000 / Revision G
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
Ordering Information
PREFIX DEVICE PACKAGE
S3041
HEATSINK
S - Integrated Circuit
3041
TF - 100 TQFP/TEP
H2 - W/DW0045-28 Heatsink Unattached
X
Prefix
XXXX
Device
XX
Package
XX
Heatsink
IS
O 90 0
D
1
IFI
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation
January 7, 2000 / Revision G
E
CE
RT
23

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